Electrostatic discharge (“ESD”) protection structures are needed for integrated circuits. In ESD protection, an ESD circuit is formed near integrated circuit terminals such as input and output pads, and also for power supply terminals. The ESD protection circuit provides a path to bypass current from the terminal to a ground or from the terminal to a power supply rail, so that the current bypasses the internal circuitry. Voltages far in excess of the operating voltages, in both positive and negative magnitudes, are observed during electrostatic discharges. The ESD protection structure prevents the voltages and corresponding current from destroying sensitive components in an integrated circuit. Advances are needed in ESD structures to prevent damage to the increasingly sensitive and ever smaller devices currently going into production and for future devices. To provide adequate protection, the ESD structures need to have low on-resistance, fast turn on speed, and be arranged to be reliably produced in the advanced semiconductor processes currently in use, without requiring significant silicon area.
Silicon controlled rectifiers (“SCRs”), which may be conveniently formed by forming parasitic transistors in doped well regions adjacent a terminal, are often used for ESD structures. Because an SCR can be designed to “trigger” on in response to a trigger voltage over a threshold, and then to safely conduct ESD stress current through an alternative path to an external terminal and thus protect the internal circuitry coupled to a pad terminal, the SCR provides many features that are desirable for ESD protection. However, the existing SCR structures also have some characteristics that are undesirable. Existing SCR circuits are subject to a “latch up” phenomenon. In latch up, the SCR may remain active following an ESD event. This condition may persist until the power to the integrated circuit is cycled, preventing the internal circuitry coupled to the terminal from operating properly. Latch up immunity is a requirement for SCR circuitry that some SCR structures implemented in the existing approaches do not provide. After the SCR circuit is triggered, it may remain active as long as a voltage over the “holding voltage” is present. If the “holding voltage” for an ESD SCR is too low, then, the SCR will likely latch up and stay active when the pad is no longer under ESD stress. Accordingly increased holding voltages in SCRs for ESD protection are desirable.
However, existing approaches to increasing the holding voltage often require additional devices, and may increase semiconductor area. Semiconductor area is a critical characteristic as integrated circuit devices continue to add additional functionality and become increasingly more highly integrated.
Improved SCR structures that are semiconductor area efficient, have excellent ESD performance including lowered holding voltages and turn on speed, have improved latch-up immunity, and which are compatible with current and future advanced semiconductor processes are therefore needed.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the illustrative embodiments and are not necessarily drawn to scale.